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--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8k is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8k;
architecture Behavioral of sort8k is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8k is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8k;
architecture Behavioral of sort8k is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
component ulight_fifo is
port (
auto_start_external_connection_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_sel_external_connection_export : out std_logic_vector(2 downto 0); -- export
counter_rx_fifo_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
counter_tx_fifo_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
data_flag_rx_external_connection_export : in std_logic_vector(8 downto 0) := (others => 'X'); -- export
data_info_external_connection_export : in std_logic_vector(13 downto 0) := (others => 'X'); -- export
data_read_en_rx_external_connection_export : out std_logic; -- export
fifo_empty_rx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_empty_tx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_full_rx_status_external_connection_export : in std_logic := 'X'; -- export
fifo_full_tx_status_external_connection_export : in std_logic := 'X'; -- export
fsm_info_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
led_pio_test_external_connection_export : out std_logic_vector(4 downto 0); -- export
link_disable_external_connection_export : out std_logic; -- export
link_start_external_connection_export : out std_logic; -- export
memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs
memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic; -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
pll_0_locked_export : out std_logic; -- export
pll_0_outclk0_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
timecode_ready_rx_external_connection_export : in std_logic := 'X'; -- export
timecode_rx_external_connection_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
timecode_tx_data_external_connection_export : out std_logic_vector(7 downto 0); -- export
timecode_tx_enable_external_connection_export : out std_logic; -- export
timecode_tx_ready_external_connection_export : in std_logic := 'X'; -- export
write_data_fifo_tx_external_connection_export : out std_logic_vector(8 downto 0); -- export
write_en_tx_external_connection_export : out std_logic -- export
);
end component ulight_fifo;
u0 : component ulight_fifo
port map (
auto_start_external_connection_export => CONNECTED_TO_auto_start_external_connection_export, -- auto_start_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_sel_external_connection_export => CONNECTED_TO_clock_sel_external_connection_export, -- clock_sel_external_connection.export
counter_rx_fifo_external_connection_export => CONNECTED_TO_counter_rx_fifo_external_connection_export, -- counter_rx_fifo_external_connection.export
counter_tx_fifo_external_connection_export => CONNECTED_TO_counter_tx_fifo_external_connection_export, -- counter_tx_fifo_external_connection.export
data_flag_rx_external_connection_export => CONNECTED_TO_data_flag_rx_external_connection_export, -- data_flag_rx_external_connection.export
data_info_external_connection_export => CONNECTED_TO_data_info_external_connection_export, -- data_info_external_connection.export
data_read_en_rx_external_connection_export => CONNECTED_TO_data_read_en_rx_external_connection_export, -- data_read_en_rx_external_connection.export
fifo_empty_rx_status_external_connection_export => CONNECTED_TO_fifo_empty_rx_status_external_connection_export, -- fifo_empty_rx_status_external_connection.export
fifo_empty_tx_status_external_connection_export => CONNECTED_TO_fifo_empty_tx_status_external_connection_export, -- fifo_empty_tx_status_external_connection.export
fifo_full_rx_status_external_connection_export => CONNECTED_TO_fifo_full_rx_status_external_connection_export, -- fifo_full_rx_status_external_connection.export
fifo_full_tx_status_external_connection_export => CONNECTED_TO_fifo_full_tx_status_external_connection_export, -- fifo_full_tx_status_external_connection.export
fsm_info_external_connection_export => CONNECTED_TO_fsm_info_external_connection_export, -- fsm_info_external_connection.export
led_pio_test_external_connection_export => CONNECTED_TO_led_pio_test_external_connection_export, -- led_pio_test_external_connection.export
link_disable_external_connection_export => CONNECTED_TO_link_disable_external_connection_export, -- link_disable_external_connection.export
link_start_external_connection_export => CONNECTED_TO_link_start_external_connection_export, -- link_start_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
pll_0_locked_export => CONNECTED_TO_pll_0_locked_export, -- pll_0_locked.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
timecode_ready_rx_external_connection_export => CONNECTED_TO_timecode_ready_rx_external_connection_export, -- timecode_ready_rx_external_connection.export
timecode_rx_external_connection_export => CONNECTED_TO_timecode_rx_external_connection_export, -- timecode_rx_external_connection.export
timecode_tx_data_external_connection_export => CONNECTED_TO_timecode_tx_data_external_connection_export, -- timecode_tx_data_external_connection.export
timecode_tx_enable_external_connection_export => CONNECTED_TO_timecode_tx_enable_external_connection_export, -- timecode_tx_enable_external_connection.export
timecode_tx_ready_external_connection_export => CONNECTED_TO_timecode_tx_ready_external_connection_export, -- timecode_tx_ready_external_connection.export
write_data_fifo_tx_external_connection_export => CONNECTED_TO_write_data_fifo_tx_external_connection_export, -- write_data_fifo_tx_external_connection.export
write_en_tx_external_connection_export => CONNECTED_TO_write_en_tx_external_connection_export -- write_en_tx_external_connection.export
);
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
entity ic74595_tb is
end ic74595_tb;
architecture behavior of ic74595_tb is
component ic74595
port (ds : in std_logic;
shcp : in std_logic;
mr : in std_logic;
stcp : in std_logic;
oe : in std_logic;
q : out std_logic_vector(7 downto 0);
q7s : out std_logic);
end component;
signal clock: std_logic := '0';
signal serial: std_logic := '0';
signal clear: std_logic := '1';
signal load: std_logic := '0';
signal oe: std_logic := '0';
signal q: std_logic_vector(0 to 7) := "00000000";
signal sout: std_logic;
for ic: ic74595 use entity work.ic74595;
begin
ic: ic74595 port map (ds => serial,
shcp => clock,
mr => clear,
stcp => load,
oe => oe,
q => q,
q7s => sout);
process
constant byte: std_logic_vector(7 downto 0) := "01001101";
begin
report "should output Z when not OE";
oe <= '1';
wait for 10 ns;
assert q = "ZZZZZZZZ" report "Q is not Z";
oe <= '0';
wait for 10 ns;
assert q /= "ZZZZZZZZ" report "Q is Z";
report "should shift some data in";
for i in byte'range loop
serial <= byte(i);
clock <= '1'; wait for 4 ns; clock <= '0'; wait for 4 ns;
end loop;
load <= '1'; wait for 4 ns; load <= '0'; wait for 4 ns;
assert q = "01001101";
report "should write rightmost bit in serial out";
assert sout = '0';
clock <= '1'; wait for 4 ns; clock <= '0'; wait for 4 ns;
assert sout = '1';
report "should clear on signal";
clear <= '0';
wait for 10 ns;
load <= '1'; wait for 4 ns; load <= '0'; wait for 4 ns;
assert q = "00000000";
report "end of test";
wait;
end process;
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc95.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p09n01i00095pkg is
type rec is record
ele1: integer;
ele2: integer;
end record;
type at is access rec;
end c04s03b02x00p09n01i00095pkg;
use work.c04s03b02x00p09n01i00095pkg.all;
ENTITY c04s03b02x00p09n01i00095ent IS
generic ( A2 : at );
END c04s03b02x00p09n01i00095ent;
ARCHITECTURE c04s03b02x00p09n01i00095arch OF c04s03b02x00p09n01i00095ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p09n01i00095 - The subtype indication for an interface constant or signal declaration can not be of access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p09n01i00095arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc95.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p09n01i00095pkg is
type rec is record
ele1: integer;
ele2: integer;
end record;
type at is access rec;
end c04s03b02x00p09n01i00095pkg;
use work.c04s03b02x00p09n01i00095pkg.all;
ENTITY c04s03b02x00p09n01i00095ent IS
generic ( A2 : at );
END c04s03b02x00p09n01i00095ent;
ARCHITECTURE c04s03b02x00p09n01i00095arch OF c04s03b02x00p09n01i00095ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p09n01i00095 - The subtype indication for an interface constant or signal declaration can not be of access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p09n01i00095arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc95.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p09n01i00095pkg is
type rec is record
ele1: integer;
ele2: integer;
end record;
type at is access rec;
end c04s03b02x00p09n01i00095pkg;
use work.c04s03b02x00p09n01i00095pkg.all;
ENTITY c04s03b02x00p09n01i00095ent IS
generic ( A2 : at );
END c04s03b02x00p09n01i00095ent;
ARCHITECTURE c04s03b02x00p09n01i00095arch OF c04s03b02x00p09n01i00095ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p09n01i00095 - The subtype indication for an interface constant or signal declaration can not be of access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p09n01i00095arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01597ent IS
END c08s11b00x00p03n01i01597ent;
ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
L1 :
for i in boolean loop
p := 5 + p;
L2 :
for j in 1 to 3 loop
exit ;
p := 0;
end loop L2 ;
end loop L1;
assert NOT( p=10 )
report "***PASSED TEST: c08s11b00x00p03n01i01597"
severity NOTE;
assert ( p=10 )
report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01597arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01597ent IS
END c08s11b00x00p03n01i01597ent;
ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
L1 :
for i in boolean loop
p := 5 + p;
L2 :
for j in 1 to 3 loop
exit ;
p := 0;
end loop L2 ;
end loop L1;
assert NOT( p=10 )
report "***PASSED TEST: c08s11b00x00p03n01i01597"
severity NOTE;
assert ( p=10 )
report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01597arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01597ent IS
END c08s11b00x00p03n01i01597ent;
ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
L1 :
for i in boolean loop
p := 5 + p;
L2 :
for j in 1 to 3 loop
exit ;
p := 0;
end loop L2 ;
end loop L1;
assert NOT( p=10 )
report "***PASSED TEST: c08s11b00x00p03n01i01597"
severity NOTE;
assert ( p=10 )
report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01597arch;
|
-- file: patternClk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity patternClk_tb is
end patternClk_tb;
architecture test of patternClk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component patternClk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : patternClk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-- file: patternClk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity patternClk_tb is
end patternClk_tb;
architecture test of patternClk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component patternClk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : patternClk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-- file: patternClk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity patternClk_tb is
end patternClk_tb;
architecture test of patternClk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component patternClk_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : patternClk_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWI_Ctl - Behavioral
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Description: TWI_Ctl is a reusabled Master Controller implementation of the
-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
-- FAST mode should also be theoretically possible, although it has not been
-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
-- buses. Slave-wait is also supported.
--
--
-- Dependencies: digilent.PkgTWI_Utils package - TWI_Ctl.vhd
--
-- Revision:
-- Revision 1.01 - Bugfix: stop condition might be prevented device read
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.all;
library digilent;
use work.PkgTWI_Utils.ALL;
entity TWI_Ctl is
----------------------------------------------------------------------------------
-- Title : Mode of operation
-- Description: The controller can be instructed to initiate/continue/stop a
-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
-- signals are synchronous to CLK and input signals must also be synchronous to
-- CLK. Signals are active-high.
-- Fast-track instructions (single byte transfer):
-- -put the TWI address on A_I
-- -if data is written put it on D_I
-- -assert STB_I
-- -when DONE_O pulse arrives, read data is present on D_O, if any
-- -repeat, or deassert STB_I
-- Detailed data transfer flow:
-- -when DONE_O is low, the controller is ready to accept commands
-- -data transfer can be initiated by putting a TWI slave address on the A_I
-- bus and providing a strobe (STB_I)
-- -the direction of data transfer (read/write) is determined by the LSB of the
-- address (0-write, 1-read)
-- -in case of a 'write' the data byte should also be present on the D_I bus
-- prior to the arrival of the strobe (STB_I)
-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
-- together with DONE_I high indicates success
-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
-- strobe can be sent; this is useful, when multiple bytes are sent/received
-- in a single transfer packet; for ex. for write transfers, a new byte can
-- be put on the D_I and STB_I provided;
-- -if no new strobe is provided, the transfer will end
-- -if a new strobe is provided, but the address changed, the current transfer
-- will end and a new will begin
-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
-- a strobe, the data byte will be written/read in a new packet; the advantage
-- of this is relevant only in multi-master buses: rather than waiting for the
-- current transfer to end and the bus to be released, a new transfer can be
-- initiated without giving up the control over the bus (STP_I=0)
-- -a new transfer with MSG_I and STB_I can be forced to issue a Stop condition
-- first, followed by a Start condition, instead of a Restart condition with
-- STP_I=1
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
--| MSG_I | STB_I | STP_I | DONE_O | ERR_O | Effect |
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
--| 0 | 0 | 0 | 0 | - | Finish current transfer (if any) and return to idle |
--| 0 | 1 | 0 | 0 | 0 | Send/receive next byte if in transfer, start new read from A_I to D_O or new write to A_I from D_I otherwise |
--| 1 | 1 | 0 | 0 | 0 | Finish current transfer (if any) and start a new one with Repeated Start |
--| 1 | 1 | 1 | 0 | 0 | Finish current transfer (if any) with Stop and start a new one with Start condition |
--| - | - | - | 1 | 0 | Current byte read/write finished, in the next cycle MSG_I/STB_I/STP_I will be read again |
--| - | - | - | 1 | 1 | Current byte read/write failed, in the next cycle MSG_I/STB_I/STP_I will be read again |
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
----------------------------------------------------------------------------------
generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
port (
MSG_I : in STD_LOGIC; --new message, has effect with STB_I=1 only
STB_I : in STD_LOGIC; --strobe
STP_I : in STD_LOGIC; --if holding bus, send stop before new message, has
--effect with STB_I=1 and MSG_I=1 only
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
ERRTYPE_O : out error_type; --error type
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
-- SDA : inout std_logic; --TWI SDA
-- SCL : inout std_logic --TWI SCL
s_scl_i : in std_logic; -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o : out std_logic; -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t : out std_logic; -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i : in std_logic; -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o : out std_logic; -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t : out std_logic -- IIC Serial Data Output Enable to 3-state buffer (required)
);
end TWI_Ctl;
architecture Behavioral of TWI_Ctl is
attribute fsm_encoding: string;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_scl_i: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_I";
ATTRIBUTE X_INTERFACE_INFO of s_scl_o: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_O";
ATTRIBUTE X_INTERFACE_INFO of s_scl_t: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_T";
ATTRIBUTE X_INTERFACE_INFO of s_sda_i: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_I";
ATTRIBUTE X_INTERFACE_INFO of s_sda_o: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_O";
ATTRIBUTE X_INTERFACE_INFO of s_sda_t: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_T";
constant FSCL : natural := 100_000; --in Hz SCL clock frequency
constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
constant TSCL_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
constant TIMEOUT_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop : std_logic;
signal busState : busState_type := busUnknown;
signal errTypeR, errType : error_type;
signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
signal slaveWait, arbLost : std_logic;
signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
signal rSda, rScl : std_logic := '1';
signal subState : unsigned(1 downto 0) := "00";
signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal int_Rst : std_logic := '0';
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of state, nstate : signal is "TRUE";
begin
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
SYNC_FFS: process(CLK)
begin
if Rising_Edge(CLK) then
dSda <= to_X01(s_sda_i);
ddSda <= to_X01(dSda);
dScl <= to_X01(s_scl_i);
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
TWISTATE: process(CLK)
begin
if Rising_Edge(CLK) then
if (int_Rst = '1') then
busState <= busUnknown;
elsif (fStart = '1') then --If START condition detected, bus is busy
busState <= busBusy;
elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
busState <= busFree;
end if;
end if;
end process;
TBUF_CNT: process(CLK)
begin
if Rising_Edge(CLK) then
if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
busFreeCnt <= TSCL_CYCLES;
elsif (dSCL = '1' and dSDA = '1') then
busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Slave devices can insert wait states by keeping SCL low
----------------------------------------------------------------------------------
slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
'0';
----------------------------------------------------------------------------------
--If the SDA line does not correspond to the transmitted data while the SCL line
--is at the HIGH level the master lost an arbitration to another master.
----------------------------------------------------------------------------------
arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
'0';
----------------------------------------------------------------------------------
-- Internal reset signal
----------------------------------------------------------------------------------
RST_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle and SRST = '0') then
int_Rst <= '0';
elsif (SRST = '1') then
int_Rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
SCL_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (sclCnt = 0 or state = stIdle) then
sclCnt <= TSCL_CYCLES/4;
elsif (slaveWait = '0') then -- clock synchronization with other masters
sclCnt <= sclCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
TIMEOUT_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (timeOutCnt = 0 or slaveWait = '0') then
timeOutCnt <= TIMEOUT_CYCLES;
elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
timeOutCnt <= timeOutCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (CLK)
begin
if Rising_Edge(CLK) then
if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
dataByte <= loadByte; --latch address/data
bitCount <= 7;
--set flag so that we know what is the byte we are sending
if (latchData = '1') then
addrNData <= '0';
else
addrNData <= '1';
end if;
elsif (shiftBit = '1' and sclCnt = 0) then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
loadByte <= A_I when latchAddr = '1' else
D_I;
dataBitOut <= dataByte(dataByte'high);
D_O <= dataByte;
----------------------------------------------------------------------------------
-- Title: Current address register
-- Description: Stores the TWI slave address
----------------------------------------------------------------------------------
CURRADDR_REG: process (CLK)
begin
if Rising_Edge(CLK) then
if (latchAddr = '1') then
currAddr <= A_I; --latch address/data
end if;
end if;
end process;
rwBit <= currAddr(0);
----------------------------------------------------------------------------------
-- Title: Substate counter
-- Description: Divides each state into 4, to respect the setup and hold times of
-- the TWI bus.
----------------------------------------------------------------------------------
SUBSTATE_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle) then
subState <= "00";
elsif (sclCnt = 0) then
subState <= subState + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
state <= nstate;
rSda <= iSda;
rScl <= iScl;
if (int_Rst = '1') then
DONE_O <= '0';
ERR_O <= '0';
errTypeR <= errType;
else
DONE_O <= iDone;
ERR_O <= iErr;
errTypeR <= errType;
end if;
end if;
end process;
OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
begin
iSda <= rSda; --no change by default
iScl <= rScl;
iDone <= '0';
iErr <= '0';
errType <= errTypeR; --keep error type
shiftBit <= '0';
latchAddr <= '0';
latchData <= '0';
if (state = stStart) then
case (subState) is
when "00" =>
iSda <= '1';
--keep SCL
when "01" =>
iSda <= '1';
iScl <= '1';
when "10" =>
iSda <= '0';
iScl <= '1';
when "11" =>
iSda <= '0';
iScl <= '0';
when others =>
end case;
end if;
if (state = stStop or state = stStopError) then
case (subState) is
when "00" =>
iSda <= '0';
--keep SCL
when "01" =>
iSda <= '0';
iScl <= '1';
when "10" =>
iSda <= '1';
iScl <= '1';
when "11" => --we will only reach this is there is an arbitration error
--keep SDA;
iScl <= '0'; --need to toggle clock
when others =>
end case;
end if;
if (state = stRead or state = stSAck) then
case (subState) is
when "00" =>
iSda <= '1'; --this will be 'Z' on SDA
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stWrite) then
case (subState) is
when "00" =>
iSda <= dataBitOut;
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMAck) then
case (subState) is
when "00" =>
iSda <= '0'; -- acknowledge by writing 0
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMNAckStop or state = stMNAckStart) then
case (subState) is
when "00" =>
iSda <= '1'; -- not acknowledge by writing 1
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stSAck and sclCnt = 0 and subState = "01") then
if (dSda = '1') then
iDone <= '1';
iErr <= '1'; --not acknowledged
errType <= errNAck;
elsif (addrNData = '0') then
--we are done only when the data is sent too after the address
iDone <= '1';
end if;
end if;
if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
iDone <= '1'; --read done
end if;
if (state = stWrite and arbLost = '1') then
iDone <= '1'; --write done
iErr <= '1'; --we lost the arbitration
errType <= errArb;
end if;
if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
shiftBit <= '1';
end if;
if (state = stStart) then
latchAddr <= '1';
end if;
if (state = stSAck and subState = "11") then --get the data byte for the next write
latchData <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I, STP_I,
SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (STB_I = '1' and busState = busFree and SRST = '0') then
nstate <= stStart;
end if;
when stStart =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (arbLost = '1') then
nstate <= stIdle;
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 0) then
nstate <= stSAck;
end if;
end if;
when stSAck =>
if (sclCnt = 0) then
if (int_Rst = '1' or (subState = "11" and dataByte(0) = '1')) then
nstate <= stStop;
elsif (subState = "11") then
if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
elsif (STB_I = '1') then -- Continue...
if (MSG_I = '1' or currAddr /= A_I) then -- ...with new transfer...
if (STP_I = '0') then -- ...by Repeated Start.
nstate <= stStart;
else -- ...by Stop and Start.
nstate <= stStop;
end if;
else -- ...with next...
if (rwBit = '1') then
nstate <= stRead; -- read byte.
else
nstate <= stWrite; -- write byte.
end if;
end if;
else -- Stop transfer.
nstate <= stStop;
end if;
end if;
end if;
when stStop =>
--bugfix: if device is driving SDA low (read transfer) we cannot send stop bit
--check the arbitration flag
if (subState = "10" and sclCnt = 0 and arbLost = '0') then
nstate <= stIdle;
end if;
--stay here, if stop bit cannot be sent, pulse clock an retry
when stRead =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 7) then --bitCount will underflow
if (STB_I = '1') then -- Continue...
if (MSG_I = '1' or currAddr /= A_I) then -- with new transfer...
if (STP_I = '0') then -- by Repeated Start.
nstate <= stMNAckStart;
else -- by Stop and Start.
nstate <= stMNAckStop;
end if;
else -- with next read byte
nstate <= stMAck;
end if;
else -- Stop transfer.
nstate <= stMNAckStop;
end if;
end if;
end if;
when stMAck =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stRead;
end if;
end if;
when stMNAckStart =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStart;
end if;
end if;
when stMNAckStop =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStop;
end if;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
-- SDA <= 'Z' when rSDA = '1' else
-- '0';
-- SCL <= 'Z' when rSCL = '1' else
-- '0';
s_sda_t <= '1' when rSDA = '1' else '0';
s_sda_o <= '0';
s_scl_o <= '0';
s_scl_t <= '1' when rSCL = '1' else '0';
end Behavioral; |
--========================================================================
-- fifo.vhd :: FIFO (16-deep)
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FIFO is
port(
FIFO_OUT : out std_logic_vector(7 downto 0);
FIFO_IN : in std_logic_vector(7 downto 0);
OVFL : out std_logic; -- overflow
LAST : out std_logic; -- nearly full
EMPTY : out std_logic; -- empty
FIFO_OP : in std_logic; -- 1==push 0==pop
CKEN : in std_logic; -- clock enable
CLK : in std_logic; -- clock
RESET : in std_logic -- Reset
);
end FIFO;
architecture BEHAVIORAL of FIFO is
signal RD_ADDR : std_logic_vector(3 downto 0);
signal WR_ADDR : std_logic_vector(3 downto 0);
signal DEPTH : std_logic_vector(3 downto 0);
type Memtype is array (integer range 0 to 15) of std_logic_vector(7 downto 0);
signal MEM : Memtype;
begin
--================================================================
-- FIFO pointers
--================================================================
FIFO_POINTERS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
-- increment write pointer on push
-- and increment the depth.. if not full (no overflow)
if ((FIFO_OP = '1') and (CKEN = '1') and (DEPTH /= "1111")) then
WR_ADDR <= WR_ADDR + 1;
DEPTH <= DEPTH + 1;
end if;
-- increment read pointer on pop
-- and decrement the depth.. if not empty (no underflow)
if ((FIFO_OP = '0') and (CKEN = '1') and (DEPTH /= "0000")) then
RD_ADDR <= RD_ADDR + 1;
DEPTH <= DEPTH - 1;
end if;
-- reset state
if (RESET = '1') then
WR_ADDR <= (others => '0');
RD_ADDR <= (others => '0');
DEPTH <= (others => '0');
end if;
end if;
end process;
--================================================================
-- FIFO flags
--================================================================
FIFO_FLAGS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
OVFL <= '0';
LAST <= '0';
EMPTY <= '0';
if (DEPTH = "1111") then
OVFL <= '1';
end if;
if ((DEPTH = "1110") or (DEPTH = "1111")) then
LAST <= '1';
end if;
if (DEPTH = "0000") then
EMPTY <= '1';
end if;
end if;
end process;
--================================================================
-- Fifo RAM
--================================================================
FIFO_RAM:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((CKEN = '1') and (FIFO_OP = '1')) then
MEM(conv_integer(WR_ADDR)) <= FIFO_IN;
end if;
if (RESET = '1') then
MEM(0) <= (others => '0');
MEM(1) <= (others => '0');
MEM(2) <= (others => '0');
MEM(3) <= (others => '0');
MEM(4) <= (others => '0');
MEM(5) <= (others => '0');
MEM(6) <= (others => '0');
MEM(7) <= (others => '0');
MEM(8) <= (others => '0');
MEM(9) <= (others => '0');
MEM(10) <= (others => '0');
MEM(11) <= (others => '0');
MEM(12) <= (others => '0');
MEM(13) <= (others => '0');
MEM(14) <= (others => '0');
MEM(15) <= (others => '0');
end if;
end if;
end process;
FIFO_OUT <= MEM(conv_integer(RD_ADDR));
end BEHAVIORAL;
|
--========================================================================
-- fifo.vhd :: FIFO (16-deep)
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FIFO is
port(
FIFO_OUT : out std_logic_vector(7 downto 0);
FIFO_IN : in std_logic_vector(7 downto 0);
OVFL : out std_logic; -- overflow
LAST : out std_logic; -- nearly full
EMPTY : out std_logic; -- empty
FIFO_OP : in std_logic; -- 1==push 0==pop
CKEN : in std_logic; -- clock enable
CLK : in std_logic; -- clock
RESET : in std_logic -- Reset
);
end FIFO;
architecture BEHAVIORAL of FIFO is
signal RD_ADDR : std_logic_vector(3 downto 0);
signal WR_ADDR : std_logic_vector(3 downto 0);
signal DEPTH : std_logic_vector(3 downto 0);
type Memtype is array (integer range 0 to 15) of std_logic_vector(7 downto 0);
signal MEM : Memtype;
begin
--================================================================
-- FIFO pointers
--================================================================
FIFO_POINTERS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
-- increment write pointer on push
-- and increment the depth.. if not full (no overflow)
if ((FIFO_OP = '1') and (CKEN = '1') and (DEPTH /= "1111")) then
WR_ADDR <= WR_ADDR + 1;
DEPTH <= DEPTH + 1;
end if;
-- increment read pointer on pop
-- and decrement the depth.. if not empty (no underflow)
if ((FIFO_OP = '0') and (CKEN = '1') and (DEPTH /= "0000")) then
RD_ADDR <= RD_ADDR + 1;
DEPTH <= DEPTH - 1;
end if;
-- reset state
if (RESET = '1') then
WR_ADDR <= (others => '0');
RD_ADDR <= (others => '0');
DEPTH <= (others => '0');
end if;
end if;
end process;
--================================================================
-- FIFO flags
--================================================================
FIFO_FLAGS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
OVFL <= '0';
LAST <= '0';
EMPTY <= '0';
if (DEPTH = "1111") then
OVFL <= '1';
end if;
if ((DEPTH = "1110") or (DEPTH = "1111")) then
LAST <= '1';
end if;
if (DEPTH = "0000") then
EMPTY <= '1';
end if;
end if;
end process;
--================================================================
-- Fifo RAM
--================================================================
FIFO_RAM:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((CKEN = '1') and (FIFO_OP = '1')) then
MEM(conv_integer(WR_ADDR)) <= FIFO_IN;
end if;
if (RESET = '1') then
MEM(0) <= (others => '0');
MEM(1) <= (others => '0');
MEM(2) <= (others => '0');
MEM(3) <= (others => '0');
MEM(4) <= (others => '0');
MEM(5) <= (others => '0');
MEM(6) <= (others => '0');
MEM(7) <= (others => '0');
MEM(8) <= (others => '0');
MEM(9) <= (others => '0');
MEM(10) <= (others => '0');
MEM(11) <= (others => '0');
MEM(12) <= (others => '0');
MEM(13) <= (others => '0');
MEM(14) <= (others => '0');
MEM(15) <= (others => '0');
end if;
end if;
end process;
FIFO_OUT <= MEM(conv_integer(RD_ADDR));
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (1 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end bcd_multiplexer;
architecture bcd_multiplexer_arq of bcd_multiplexer is
begin
process (mux_selector,bcd0_input,bcd1_input,bcd2_input,bcd3_input) is
begin
case mux_selector is
when "00" => mux_output <= bcd0_input;
when "01" => mux_output <= bcd1_input;
when "10" => mux_output <= bcd2_input;
when "11" => mux_output <= bcd3_input;
when others => mux_output <= (others => '0');
end case;
end process;
end bcd_multiplexer_arq;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1200.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p07n01i01200ent IS
END c08s01b00x00p07n01i01200ent;
ARCHITECTURE c08s01b00x00p07n01i01200arch OF c08s01b00x00p07n01i01200ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable j : integer := 0;
BEGIN
k <= 5 after 5 ns;
j := 5;
wait for j;
assert FALSE
report "***FAILED TEST: c08s01b00x00p07n01i01200 - Time expression is missing in the timeout expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p07n01i01200arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1200.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p07n01i01200ent IS
END c08s01b00x00p07n01i01200ent;
ARCHITECTURE c08s01b00x00p07n01i01200arch OF c08s01b00x00p07n01i01200ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable j : integer := 0;
BEGIN
k <= 5 after 5 ns;
j := 5;
wait for j;
assert FALSE
report "***FAILED TEST: c08s01b00x00p07n01i01200 - Time expression is missing in the timeout expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p07n01i01200arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1200.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p07n01i01200ent IS
END c08s01b00x00p07n01i01200ent;
ARCHITECTURE c08s01b00x00p07n01i01200arch OF c08s01b00x00p07n01i01200ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
variable j : integer := 0;
BEGIN
k <= 5 after 5 ns;
j := 5;
wait for j;
assert FALSE
report "***FAILED TEST: c08s01b00x00p07n01i01200 - Time expression is missing in the timeout expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p07n01i01200arch;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Multiply the filter coefficients with the input data and accumulate
-- the results.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_filter_mac is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Decoded data
data_i : in signed(6 downto 0);
-- Coefficient
coeff_i : in unsigned(23 downto 0);
coeff_en_i : in std_ulogic;
coeff_done_i : in std_ulogic;
-- MAC result
data_o : out signed(23 downto 0);
data_en_o : out std_ulogic);
end entity ads1281_filter_mac;
architecture rtl of ads1281_filter_mac is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal res : signed(30 downto 0);
signal res_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Multiply filter coefficient with input data
ads1281_filter_multiplier_inst : entity work.ads1281_filter_multiplier
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => data_i,
coeff_i => coeff_i,
coeff_en_i => coeff_en_i,
res_o => res,
res_en_o => res_en);
-- Accumulate result
ads1281_filter_accumulator_inst : entity work.ads1281_filter_accumulator
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => res,
data_en_i => res_en,
coeff_done_i => coeff_done_i,
data_o => data_o,
data_en_o => data_en_o);
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block5.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block5
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_15_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_15_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_13_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_14_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_14_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_13_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block5;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block5 IS
-- Component Declarations
COMPONENT Complex3Multiply_block8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_14_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block8
USE ENTITY work.Complex3Multiply_block8(rtl);
-- Signals
SIGNAL dout_13_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_13_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_15_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_15_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_14_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_14_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_2 : Complex3Multiply_block8
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
softReset => softReset,
twdlXdin_14_re => twdlXdin_14_re_tmp, -- sfix19_En13
twdlXdin_14_im => twdlXdin_14_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_13_vld
);
dout_13_re_signed <= signed(dout_13_re);
din_re <= resize(dout_13_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_13_re <= std_logic_vector(din1_re_dly9);
dout_13_im_signed <= signed(dout_13_im);
din_im <= resize(dout_13_im_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_13_im <= std_logic_vector(din1_im_dly9);
dout_15_re_signed <= signed(dout_15_re);
din_re_1 <= resize(dout_15_re_signed, 19);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_15_im_signed <= signed(dout_15_im);
din_im_1 <= resize(dout_15_im_signed, 19);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_14_re <= twdlXdin_14_re_tmp;
twdlXdin_14_im <= twdlXdin_14_im_tmp;
END rtl;
|
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect_wrapper.bd
--Design : DemoInterconnect_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_wrapper is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
end DemoInterconnect_wrapper;
architecture STRUCTURE of DemoInterconnect_wrapper is
component DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
sys_clk : in STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
sys_reset : in STD_LOGIC
);
end component DemoInterconnect;
begin
DemoInterconnect_i: component DemoInterconnect
port map (
LED0_pll_aclk => LED0_pll_aclk,
LED1_pll_uart => LED1_pll_uart,
LED2_pll_lock => LED2_pll_lock,
UART_RX_0 => UART_RX_0,
UART_RX_1 => UART_RX_1,
UART_TX_0 => UART_TX_0,
UART_TX_1 => UART_TX_1,
m_spi_miso => m_spi_miso,
m_spi_miso_1 => m_spi_miso_1,
m_spi_miso_2 => m_spi_miso_2,
m_spi_miso_3 => m_spi_miso_3,
m_spi_mosi => m_spi_mosi,
m_spi_mosi_1 => m_spi_mosi_1,
m_spi_mosi_2 => m_spi_mosi_2,
m_spi_mosi_3 => m_spi_mosi_3,
m_spi_sclk => m_spi_sclk,
m_spi_sclk_1 => m_spi_sclk_1,
m_spi_sclk_2 => m_spi_sclk_2,
m_spi_sclk_3 => m_spi_sclk_3,
m_spi_ss => m_spi_ss,
m_spi_ss_1 => m_spi_ss_1,
m_spi_ss_2 => m_spi_ss_2,
m_spi_ss_3 => m_spi_ss_3,
sys_clk => sys_clk,
sys_reset => sys_reset
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_377 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_377;
architecture augh of sub_377 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_377 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_377;
architecture augh of sub_377 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
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-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
-- adder_tree.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder_tree is
generic (
INPUT_COUNT : integer := 9;
DATA_WIDTH : integer := 8
);
port (
CLK : in std_logic;
CE : in std_logic;
DIN : in std_logic_vector(INPUT_COUNT * DATA_WIDTH - 1 downto 0);
DOUT : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture full of adder_tree is
constant LEFT_COUNT : integer := INPUT_COUNT / 2 + INPUT_COUNT mod 2;
constant RIGHT_COUNT : integer := INPUT_COUNT / 2;
constant LEFT_BEG : integer := INPUT_COUNT;
constant LEFT_END : integer := INPUT_COUNT - LEFT_COUNT;
constant RIGHT_BEG : integer := LEFT_END;
constant RIGHT_END : integer := 0;
signal left_din : std_logic_vector(LEFT_COUNT * DATA_WIDTH - 1 downto 0);
signal right_din : std_logic_vector(RIGHT_COUNT * DATA_WIDTH - 1 downto 0);
signal left_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal right_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
assert INPUT_COUNT > 0
report "INPUT_COUNT must be greater then 0 to make sense"
severity failure;
assert RIGHT_BEG - RIGHT_END = RIGHT_COUNT
report "BUG: invalid RIGHT_* computation for " & integer'image(INPUT_COUNT) & " inputs"
severity failure;
assert LEFT_BEG - LEFT_END = LEFT_COUNT
report "BUG: invalid LEFT_* computation for " & integer'image(INPUT_COUNT) & " inputs"
severity failure;
---------------------------------------
gen_register: if INPUT_COUNT = 1
generate
add_op : process(CLK, DIN, CE)
begin
if rising_edge(CLK) then
if CE = '1' then
DOUT <= DIN;
end if;
end if;
end process;
end generate;
---------------------------------------
gen_simple_add: if INPUT_COUNT = 2
generate
add_op : process(CLK, DIN, CE)
begin
if rising_edge(CLK) then
if CE = '1' then
DOUT <= DIN(DATA_WIDTH - 1 downto 0) + DIN(DATA_WIDTH * 2 - 1 downto DATA_WIDTH);
end if;
end if;
end process;
end generate;
---------------------------------------
gen_tree: if INPUT_COUNT > 2
generate
left_i : entity work.adder_tree(full)
generic map (
INPUT_COUNT => LEFT_COUNT,
DATA_WIDTH => DATA_WIDTH
)
port map (
CLK => CLK,
CE => CE,
DIN => left_din,
DOUT => left_dout
);
left_din <= DIN(LEFT_BEG * DATA_WIDTH - 1 downto LEFT_END * DATA_WIDTH);
--------------------
right_i : entity work.adder_tree
generic map (
INPUT_COUNT => RIGHT_COUNT,
DATA_WIDTH => DATA_WIDTH
)
port map (
CLK => CLK,
CE => CE,
DIN => right_din,
DOUT => right_dout
);
right_din <= DIN(RIGHT_BEG * DATA_WIDTH - 1 downto RIGHT_END * DATA_WIDTH);
--------------------
add_levels : process(CLK, left_dout, right_dout, CE)
begin
if rising_edge(CLK) then
if CE = '1' then
DOUT <= left_dout + right_dout;
end if;
end if;
end process;
end generate;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
oV1KAJ+dthMXwrYccVUqx0U/KE0JaRwSUlh+Jmr4hnKTbyVwLMWEOVaJD7Zx8bGVzO9fFbI5YjTM
pZr7cIUZEw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OKI9T0Ejg+B5viTq13j4yv9QyDhYTqJEMHtOygg2Hr4WnzzZERNoiJi5TMNEOTHg4q7HROiMXTA9
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5648)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5648)
`protect data_block
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`protect end_protected
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_2;
USE fifo_generator_v13_1_2.fifo_generator_v13_1_2;
ENTITY fifo_generator_0 IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_2 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_v13_1_2,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_0_arch : ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0," &
"C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_" &
"FULL_THRESH_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2," &
"C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_R" &
"USER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTA" &
"TION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WA" &
"CH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH" &
"_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL" &
"_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THR" &
"ESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_2
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:14:02 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab-rtl-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_ab-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ab
--
architecture rtl of inst_ab is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
--
-- Title : ethrx_zcpsm
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethrx_zcpsm is
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end ethrx_zcpsm;
--}} End of automatically maintained section
architecture behavior of ethrx_zcpsm is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component ethrxrom_romonly
port(
addrb : in std_logic_vector(11 downto 0);
clkb : in std_logic;
dob : out std_logic_vector(17 downto 0));
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
begin
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rx_rom : ethrxrom_romonly
port map(
addrb => address,
clkb => clk,
dob => instruction
);
end behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2220.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02220ent IS
END c07s02b06x00p01n01i02220ent;
ARCHITECTURE c07s02b06x00p01n01i02220arch OF c07s02b06x00p01n01i02220ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod BITV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02220 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02220arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2220.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02220ent IS
END c07s02b06x00p01n01i02220ent;
ARCHITECTURE c07s02b06x00p01n01i02220arch OF c07s02b06x00p01n01i02220ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod BITV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02220 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02220arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2220.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02220ent IS
END c07s02b06x00p01n01i02220ent;
ARCHITECTURE c07s02b06x00p01n01i02220arch OF c07s02b06x00p01n01i02220ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV mod BITV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02220 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02220arch;
|
-------------------------------------------------------------------------------
-- Title : Single port cache
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : SinglePort_Cache.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-19
-- Last update: 2016-11-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Cache with one access port and one port to the memory/L+1 cache
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-19 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity SinglePort_Cache is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port (
clk : in std_logic;
rst : in std_logic;
i_porta_req : in std_logic;
i_porta_we : in std_logic;
i_porta_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_porta_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
o_porta_valid : out std_logic;
o_memory_req : out std_logic;
o_memory_we : out std_logic;
o_memory_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_memory_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
i_memory_valid : in std_logic
);
end entity SinglePort_Cache;
-------------------------------------------------------------------------------
architecture passthrough of SinglePort_Cache is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
-- access handling
signal cache_initialized : boolean := false;
signal cache_loaded : boolean;
signal cache_hit : boolean;
signal cache_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := (others => '1');
signal cache_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
-- cache_valid means: for previously latched address, cache_data is valid.
-- cache_valid also means: for last time i_porta_req was raised, for the
-- i_porta_addr that was input, the data on cache_data is valid.
signal cache_valid : boolean;
-- dearm_memory_req : ensure o_memory_req is held only 1 cycle for each request
signal dearm_memory_req : boolean := false;
signal memory_ongoing : boolean := false;
begin -- architecture str
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
process(rst, clk) is
begin
if rst = '0' then
if rising_edge(clk) then
if i_porta_req = '1' then
if not cache_initialized or cache_addr /= i_porta_addr then
cache_addr <= i_porta_addr;
cache_valid <= false;
cache_data <= (others => 'X');
o_memory_addr <= i_porta_addr;
o_memory_req <= '1';
dearm_memory_req <= true;
memory_ongoing <= true;
o_memory_we <= i_porta_we;
o_memory_write_data <= i_porta_write_data;
end if;
-- If cache_valid and cache_valid = i_porta_addr, output is still
-- valid and nothing is to be done.
elsif dearm_memory_req then
o_memory_req <= '0';
dearm_memory_req <= false;
if i_memory_valid = '0' then
cache_valid <= false; -- dearm cache_valid one cycle after
-- cache_addr changed
end if;
end if;
if i_memory_valid = '1' then
memory_ongoing <= false;
cache_data <= i_memory_read_data;
cache_initialized <= true;
if not (i_porta_req = '1' and (cache_addr /= i_porta_addr)) then
cache_valid <= true;
end if;
-- In parallel, o_porta_valid will become '1'
end if;
end if;
else
o_memory_req <= '0';
cache_valid <= false;
end if;
end process;
o_porta_valid <= '1' when cache_valid else '0';
o_porta_read_data <= cache_data when cache_valid else (others => 'X');
end architecture passthrough;
---------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when slew = 0 else i;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when slew = 0 else i;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_25Mhz : IN STD_LOGIC;
clock_12Mhz : OUT STD_LOGIC;
clock_6Mhz : OUT STD_LOGIC;
clock_3Mhz : OUT STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC
);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int, clock_12Mhz_int, clock_6Mhz_int, clock_3Mhz_int : STD_LOGIC;
BEGIN
PROCESS -- 25 divide by 2
BEGIN
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
clock_12Mhz_int <= not clock_12Mhz_int;
END PROCESS;
PROCESS -- 12 divide by 2
BEGIN
WAIT UNTIL clock_12Mhz_int'EVENT and clock_12Mhz_int = '1';
clock_6Mhz_int <= not clock_6Mhz_int;
END PROCESS;
PROCESS -- 6 divide by 2
BEGIN
WAIT UNTIL clock_6Mhz_int'EVENT and clock_6Mhz_int = '1';
clock_3Mhz_int <= not clock_3Mhz_int;
END PROCESS;
PROCESS
BEGIN
-- Divide by 25
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
IF count_1Mhz < 24 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "00000";
END IF;
IF count_1Mhz < 12 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
clock_12Mhz <= clock_12Mhz_int;
clock_3Mhz <= clock_3Mhz_int;
clock_1Mhz <= clock_1Mhz_int;
clock_100Khz <= clock_100Khz_int;
clock_10Khz <= clock_10Khz_int;
clock_1Khz <= clock_1Khz_int;
clock_100hz <= clock_100hz_int;
clock_10hz <= clock_10hz_int;
clock_6Mhz <= clock_6Mhz_int;
clock_1hz <= clock_1hz_int;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
IF count_100Khz /= 4 THEN
count_100Khz <= count_100Khz + 1;
ELSE
count_100khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_25Mhz : IN STD_LOGIC;
clock_12Mhz : OUT STD_LOGIC;
clock_6Mhz : OUT STD_LOGIC;
clock_3Mhz : OUT STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC
);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int, clock_12Mhz_int, clock_6Mhz_int, clock_3Mhz_int : STD_LOGIC;
BEGIN
PROCESS -- 25 divide by 2
BEGIN
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
clock_12Mhz_int <= not clock_12Mhz_int;
END PROCESS;
PROCESS -- 12 divide by 2
BEGIN
WAIT UNTIL clock_12Mhz_int'EVENT and clock_12Mhz_int = '1';
clock_6Mhz_int <= not clock_6Mhz_int;
END PROCESS;
PROCESS -- 6 divide by 2
BEGIN
WAIT UNTIL clock_6Mhz_int'EVENT and clock_6Mhz_int = '1';
clock_3Mhz_int <= not clock_3Mhz_int;
END PROCESS;
PROCESS
BEGIN
-- Divide by 25
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
IF count_1Mhz < 24 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "00000";
END IF;
IF count_1Mhz < 12 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
clock_12Mhz <= clock_12Mhz_int;
clock_3Mhz <= clock_3Mhz_int;
clock_1Mhz <= clock_1Mhz_int;
clock_100Khz <= clock_100Khz_int;
clock_10Khz <= clock_10Khz_int;
clock_1Khz <= clock_1Khz_int;
clock_100hz <= clock_100hz_int;
clock_10hz <= clock_10hz_int;
clock_6Mhz <= clock_6Mhz_int;
clock_1hz <= clock_1hz_int;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
IF count_100Khz /= 4 THEN
count_100Khz <= count_100Khz + 1;
ELSE
count_100khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
|
-------------------------------------------------------------------------------
--
-- The decoder unit.
-- Implements the instruction opcodes and controls all units of the T400 core.
--
-- $Id: t400_decoder.vhd,v 1.7 2008-05-01 19:49:55 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_decoder is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
out_en_i : in boolean;
in_en_i : in boolean;
icyc_en_i : in boolean;
-- Module Control Interface -----------------------------------------------
pc_op_o : out pc_op_t;
stack_op_o : out stack_op_t;
dmem_op_o : out dmem_op_t;
b_op_o : out b_op_t;
skip_op_o : out skip_op_t;
alu_op_o : out alu_op_t;
io_l_op_o : out io_l_op_t;
io_d_op_o : out io_d_op_t;
io_g_op_o : out io_g_op_t;
io_in_op_o : out io_in_op_t;
sio_op_o : out sio_op_t;
dec_data_o : out dec_data_t;
en_o : out dw_t;
-- Skip Interface ---------------------------------------------------------
skip_i : in boolean;
skip_lbi_i : in boolean;
is_lbi_o : out boolean;
int_i : in boolean;
-- Program Memory Interface -----------------------------------------------
pm_addr_i : in pc_t;
pm_data_i : in byte_t
);
end t400_decoder;
library ieee;
use ieee.numeric_std.all;
use work.t400_mnemonic_pack.all;
architecture rtl of t400_decoder is
signal cyc_cnt_q : unsigned(2 downto 0);
signal ibyte1_q,
ibyte2_q : byte_t;
signal opcode_s : byte_t;
signal second_cyc_q : boolean;
signal mnemonic_rec_s : mnemonic_rec_t;
signal mnemonic_s,
mnemonic_q : mnemonic_t;
signal multi_byte_s,
multi_byte_q : boolean;
signal last_cycle_s : boolean;
signal force_mc_s : boolean;
signal en_q : dw_t;
signal set_en_s : boolean;
signal ack_int_s : boolean;
begin
-----------------------------------------------------------------------------
-- Theory of operation:
--
-- a) One instruction cycle lasts at least 4 ck_i cycles.
-- b) PC for instruction/parameter fetch must be valid during cycle 2.
-- => cycle 2 is the opcode fetch cycle
-- c) Cycle 3 is the opcode decode cycle.
-- => opcode_s is valid with cycle 3
-- d) mnemonic_q is then valid with cycle 0 until end of instruction.
-- So is ibyte1_q.
-- e) PC for is incremented during last instruction cycle.
-- => fetch of either new instruction or second instruction byte
-- f) Second instruction byte is saved in ibyte2_q for cycle 0.
-- Valid until end of instruction.
--
-- Constraints:
--
-- a) PC of next instruction must be pushed in cycle 0 or 1.
-- b) PC for next instruction must be poped latest in cycle 1.
-- c) PC for next instruction can only be calculated latest in cycle 1.
-- d) IO output is enabled by out_en_i
-- e) IO inputs are sampled with in_en_i
--
-- d) and e) are required for proper timing in relation to phi1
-- (SK clock/sync output).
--
-- Conventions:
--
-- a) ALU operations take place in cycle 1.
--
-----------------------------------------------------------------------------
last_cycle_s <= (not multi_byte_q and
not second_cyc_q and not force_mc_s)
or
second_cyc_q;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the various sequential elements.
-- Cycle counter:
-- It identifies the execution cycle of the
-- current instruction.
-- Instruction registers:
-- They save the first and second byte of an instruction for
-- further processing.
-- New instruction flag:
-- Indicates when a new instruction is fetched from the program
-- memory. Implemented as a flip-flop to control the multiplexer
-- which saves power by gating the combinational opcode decoder.
-- Mnemonic register:
-- Latches the decoded mnemonic of the current instruction.
-- Multi byte flag:
-- Latches the decoded multi byte status information.
--
seq: process (ck_i, por_i)
begin
if por_i then
cyc_cnt_q <= to_unsigned(1, cyc_cnt_q'length);
second_cyc_q <= false;
ibyte1_q <= (others => '0');
ibyte2_q <= (others => '0');
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
en_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
mnemonic_q <= MN_CLRA;
multi_byte_q <= false;
cyc_cnt_q <= (others => '0');
en_q <= (others => '0');
elsif ck_en_i then
-- cycle counter ------------------------------------------------------
if icyc_en_i then
-- new instruction cycle started
cyc_cnt_q <= (others => '0');
elsif cyc_cnt_q /= 4 then
cyc_cnt_q <= cyc_cnt_q + 1;
end if;
-- second cycle flag --------------------------------------------------
if icyc_en_i then
if not last_cycle_s then
second_cyc_q <= true;
else
second_cyc_q <= false;
end if;
end if;
-- instruction byte 1 and mnemonic info -------------------------------
if icyc_en_i and last_cycle_s then
if not ack_int_s then
-- update instruction descriptors in normal mode
ibyte1_q <= pm_data_i;
mnemonic_q <= mnemonic_s;
multi_byte_q <= multi_byte_s;
else
-- force NOP instruction when vectoring to interrupt routine
ibyte1_q <= "01000100";
mnemonic_q <= MN_NOP;
multi_byte_q <= false;
end if;
end if;
-- instruction byte 2 -------------------------------------------------
if icyc_en_i and not last_cycle_s then
ibyte2_q <= pm_data_i;
end if;
-- EN register --------------------------------------------------------
if set_en_s then
en_q <= ibyte2_q(dw_range_t);
elsif ack_int_s then
-- reset interrupt enable when INT has been acknowledged
en_q(1) <= '0';
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Opcode multiplexer
-----------------------------------------------------------------------------
opcode_s <= pm_data_i
when icyc_en_i else
ibyte1_q;
-----------------------------------------------------------------------------
-- Opcode decoder table
--
mnemonic_rec_s <= decode_opcode_f(opcode => opcode_s,
opt_type => opt_type_g);
--
mnemonic_s <= mnemonic_rec_s.mnemonic;
multi_byte_s <= mnemonic_rec_s.multi_byte;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process decoder_ctrl
--
-- Purpose:
-- Implements the controlling logic of the decoder module.
--
decoder_ctrl: process (icyc_en_i,
out_en_i, in_en_i,
cyc_cnt_q,
mnemonic_q, second_cyc_q, last_cycle_s,
ibyte1_q, ibyte2_q,
skip_i, skip_lbi_i,
en_q, int_i,
pm_addr_i, pm_data_i)
variable cyc_v : natural range 0 to 4;
variable t41x_type_v,
t420_type_v : boolean;
variable en_int_v : boolean;
begin
-- default assignments
pc_op_o <= PC_NONE;
stack_op_o <= STACK_NONE;
dmem_op_o <= DMEM_RB; -- default is read via B
b_op_o <= B_NONE;
skip_op_o <= SKIP_NONE;
alu_op_o <= ALU_NONE;
io_l_op_o <= IOL_NONE;
io_d_op_o <= IOD_NONE;
io_g_op_o <= IOG_NONE;
io_in_op_o <= IOIN_NONE;
sio_op_o <= SIO_NONE;
dec_data_o <= (others => '0');
is_lbi_o <= false;
set_en_s <= false;
force_mc_s <= false;
en_int_v := true;
ack_int_s <= false;
cyc_v := to_integer(cyc_cnt_q);
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
t420_type_v := opt_type_g = t400_opt_type_420_c;
if icyc_en_i then
-- immediately increment program counter
-- this happens at two occasions:
-- a) right before new mnemonic becomes valid
-- b) before the second instruction cycle begins
pc_op_o <= PC_INC_PC;
end if;
if icyc_en_i and last_cycle_s then
-- update skip state when last instruction cycle ends
skip_op_o <= SKIP_UPDATE;
end if;
-- skip instruction execution
if not skip_i then
-- implement instruction control
case mnemonic_q is
-- Mnemonic ASC -------------------------------------------------------
when MN_ASC =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic ADD -------------------------------------------------------
when MN_ADD =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD;
end if;
-- Mnemonic ADT -------------------------------------------------------
when MN_ADT =>
if cyc_v = 1 then
alu_op_o <= ALU_ADD_10;
end if;
-- Mnemonic AISC ------------------------------------------------------
when MN_AISC =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_ADD_DEC;
skip_op_o <= SKIP_CARRY;
end if;
-- Mnemonic CASC ------------------------------------------------------
when MN_CASC =>
case cyc_v is
when 0 =>
alu_op_o <= ALU_COMP;
when 1 =>
alu_op_o <= ALU_ADD_C;
skip_op_o <= SKIP_CARRY;
when others =>
null;
end case;
-- Mnemonic CLRA ------------------------------------------------------
when MN_CLRA =>
if cyc_v = 1 then
alu_op_o <= ALU_CLRA;
end if;
-- Mnemonic COMP ------------------------------------------------------
when MN_COMP =>
if cyc_v = 1 then
alu_op_o <= ALU_COMP;
end if;
-- Mnemonic NOP -------------------------------------------------------
when MN_NOP =>
-- do nothing
null;
-- Mnemonic C ---------------------------------------------------------
when MN_C =>
if cyc_v = 1 then
if ibyte1_q(4) = '1' then
alu_op_o <= ALU_RC;
else
alu_op_o <= ALU_SC;
end if;
end if;
-- Mnemonic XOR -------------------------------------------------------
when MN_XOR =>
if cyc_v = 1 then
alu_op_o <= ALU_XOR;
end if;
-- Mnemonic JID -------------------------------------------------------
when MN_JID =>
force_mc_s <= true;
en_int_v := false;
dec_data_o(byte_t'range) <= pm_data_i;
if cyc_v = 1 then
if not second_cyc_q then
-- first cycle: load PC from A and M
pc_op_o <= PC_LOAD_A_M;
else
-- second cycle: load PC from program memory
pc_op_o <= PC_LOAD_8;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic JMP -------------------------------------------------------
when MN_JMP =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
end if;
-- Mnemonic JP_JSRP ---------------------------------------------------
when MN_JP_JSRP =>
en_int_v := false;
-- universal decoder data
dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
if cyc_v = 1 then
if pm_addr_i(9 downto 7) = "001" then
-- JP within pages 2 & 3
pc_op_o <= PC_LOAD_7;
elsif ibyte1_q(6) = '1' then
-- JP outside of pages 2 & 3
pc_op_o <= PC_LOAD_6;
else
-- JSRP to page 2
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
end if;
-- Mnemonic JSR -------------------------------------------------------
when MN_JSR =>
en_int_v := false;
dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
if second_cyc_q and cyc_v = 1 then
pc_op_o <= PC_LOAD;
stack_op_o <= STACK_PUSH;
end if;
-- Mnemonic RET -------------------------------------------------------
when MN_RET =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
if t420_type_v then
-- always restore skip state in case this was an interrupt
skip_op_o <= SKIP_POP;
end if;
end if;
-- Mnemonic RETSK -----------------------------------------------------
when MN_RETSK =>
en_int_v := false;
if cyc_v = 1 then
pc_op_o <= PC_POP;
stack_op_o <= STACK_POP;
skip_op_o <= SKIP_NOW;
end if;
-- Mnemonic LD --------------------------------------------------------
when MN_LD =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic LDD_XAD ---------------------------------------------------
when MN_LDD_XAD =>
-- preload decoder data
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
if second_cyc_q then
case ibyte2_q(7 downto 6) is
-- LDD
when "00" =>
if not t41x_type_v then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
when others =>
null;
end case;
end if;
-- XAD
when "10" =>
if not t41x_type_v or
unsigned(ibyte2_q(b_range_t)) = 63 then
case cyc_v is
when 1 =>
dmem_op_o <= DMEM_RDEC;
when 2 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WDEC_SRC_A;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
end if;
-- Mnemonic LQID ------------------------------------------------------
when MN_LQID =>
force_mc_s <= true;
en_int_v := false;
if not second_cyc_q then
-- first cycle: push PC and set PC from A/M,
-- read IOL from program memory
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
pc_op_o <= PC_LOAD_A_M;
end if;
if out_en_i then
io_l_op_o <= IOL_LOAD_PM;
end if;
else
if cyc_v = 1 then
-- second cycle: pop PC
stack_op_o <= STACK_POP;
pc_op_o <= PC_POP;
end if;
end if;
if icyc_en_i and not second_cyc_q then
-- do not increment PC for second instruction cycle
pc_op_o <= PC_NONE;
end if;
-- Mnemonic RMB -------------------------------------------------------
when MN_RMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_RES_BIT;
-- select bit to be reset
case ibyte1_q(dw_range_t) is
when "1100" =>
dec_data_o(dw_range_t) <= "0001";
when "0101" =>
dec_data_o(dw_range_t) <= "0010";
when "0010" =>
dec_data_o(dw_range_t) <= "0100";
when "0011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SMB -------------------------------------------------------
when MN_SMB =>
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SET_BIT;
-- select bit to be set
case ibyte1_q(dw_range_t) is
when "1101" =>
dec_data_o(dw_range_t) <= "0001";
when "0111" =>
dec_data_o(dw_range_t) <= "0010";
when "0110" =>
dec_data_o(dw_range_t) <= "0100";
when "1011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic STII ------------------------------------------------------
when MN_STII =>
dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
if cyc_v = 1 then
dmem_op_o <= DMEM_WB_SRC_DEC;
b_op_o <= B_INC_BD;
end if;
-- Mnemonic X ---------------------------------------------------------
when MN_X =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_XOR_BR;
end if;
-- Mnemonic XDS -------------------------------------------------------
when MN_XDS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_DEC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_UFLOW;
when others =>
null;
end case;
-- Mnemonic XIS -------------------------------------------------------
when MN_XIS =>
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
case cyc_v is
when 1 =>
alu_op_o <= ALU_LOAD_M;
dmem_op_o <= DMEM_WB_SRC_A;
b_op_o <= B_INC_BD;
when 2 =>
b_op_o <= B_XOR_BR;
skip_op_o <= SKIP_BD_OFLOW;
when others =>
null;
end case;
-- Mnemonic CAB -------------------------------------------------------
when MN_CAB =>
if cyc_v = 1 then
b_op_o <= B_SET_BD;
end if;
-- Mnemonic CBA -------------------------------------------------------
when MN_CBA =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BD;
end if;
-- Mnemonic LBI -------------------------------------------------------
when MN_LBI =>
is_lbi_o <= true;
en_int_v := false;
dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
if cyc_v = 1 and not skip_lbi_i then
-- increment Bd by 1
b_op_o <= B_SET_B_INC;
skip_op_o <= SKIP_LBI;
end if;
-- Mnemonic XABR ------------------------------------------------------
when MN_XABR =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_BR;
b_op_o <= B_SET_BR;
end if;
-- Mnemonic SKC -------------------------------------------------------
when MN_SKC =>
if cyc_v = 1 then
skip_op_o <= SKIP_C;
end if;
-- Mnemonic SKE -------------------------------------------------------
when MN_SKE =>
if cyc_v = 1 then
skip_op_o <= SKIP_A_M;
end if;
-- Mnemonic SKMBZ -----------------------------------------------------
when MN_SKMBZ =>
if cyc_v = 1 then
skip_op_o <= SKIP_M_BIT;
-- select bit to be checked
case ibyte1_q is
when "00000001" =>
dec_data_o(dw_range_t) <= "0001";
when "00010001" =>
dec_data_o(dw_range_t) <= "0010";
when "00000011" =>
dec_data_o(dw_range_t) <= "0100";
when "00010011" =>
dec_data_o(dw_range_t) <= "1000";
when others =>
null;
end case;
end if;
-- Mnemonic SKT -------------------------------------------------------
when MN_SKT =>
if cyc_v = 1 then
skip_op_o <= SKIP_TIMER;
end if;
-- Mnemonic XAS -------------------------------------------------------
when MN_XAS =>
if out_en_i then
sio_op_o <= SIO_LOAD;
alu_op_o <= ALU_LOAD_SIO;
end if;
-- Mnemonic EXT -------------------------------------------------------
when MN_EXT =>
if second_cyc_q then
case ibyte2_q is
-- CAMQ
when "00111100" =>
if out_en_i then
io_l_op_o <= IOL_LOAD_AM;
end if;
-- CQMA
when "00101100" =>
if not t41x_type_v and in_en_i then
io_l_op_o <= IOL_OUTPUT_Q;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- SKGZ
when "00100001" =>
if in_en_i then
skip_op_o <= SKIP_G_ZERO;
end if;
-- SKGBZ
when "00000001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0001";
end if;
when "00010001" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0010";
end if;
when "00000011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "0100";
end if;
when "00010011" =>
if in_en_i then
skip_op_o <= SKIP_G_BIT;
dec_data_o(dw_range_t) <= "1000";
end if;
-- ING
when "00101010" =>
if cyc_v = 1 then
alu_op_o <= ALU_LOAD_G;
end if;
-- INL
when "00101110" =>
if in_en_i then
io_l_op_o <= IOL_OUTPUT_L;
alu_op_o <= ALU_LOAD_Q;
dmem_op_o <= DMEM_WB_SRC_Q;
end if;
-- ININ
when "00101000" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IN;
end if;
-- INIL
when "00101001" =>
if not t41x_type_v and in_en_i then
alu_op_o <= ALU_LOAD_IL;
io_in_op_o <= IOIN_INIL;
end if;
-- OBD
when "00111110" =>
if out_en_i then
io_d_op_o <= IOD_LOAD;
end if;
-- OMG
when "00111010" =>
if out_en_i then
io_g_op_o <= IOG_LOAD_M;
end if;
-- multiple codes
when others =>
-- apply default decoder output, largest required vector
dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
-- LBI
if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
is_lbi_o <= true;
en_int_v := false;
if cyc_v > 0 and not skip_lbi_i then
b_op_o <= B_SET_B;
skip_op_o <= SKIP_LBI;
end if;
end if;
-- LEI
if ibyte2_q(7 downto 4) = "0110" and in_en_i then
-- dec_data_o applied by default
set_en_s <= true;
-- acknowledge pending interrupt when EN(1) is not
-- enabled - will clear them until interrupts are
-- enabled with EN(1) = '1'
if en_q(1) = '0' then
io_in_op_o <= IOIN_INTACK;
end if;
end if;
-- OGI
if ibyte2_q(7 downto 4) = "0101" and out_en_i and
not t41x_type_v then
-- dec_data_o applied by default
io_g_op_o <= IOG_LOAD_DEC;
end if;
end case;
end if;
when others =>
null;
end case;
end if;
-- Interrupt handling -----------------------------------------------------
if t420_type_v and
en_q(1) = '1' and int_i and en_int_v then
if last_cycle_s then
if cyc_v = 1 then
stack_op_o <= STACK_PUSH;
end if;
if icyc_en_i then
ack_int_s <= true;
io_in_op_o <= IOIN_INTACK;
pc_op_o <= PC_INT;
-- push skip state that was determined by current instruction
-- and will be valid for the next instruction which is delayed
-- by the interrupt
skip_op_o <= SKIP_PUSH;
end if;
end if;
end if;
end process decoder_ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
en_o <= en_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.5 2006/05/28 15:32:14 arniml
-- execute virtual NOP at location 0x0ff when vectoring to interrupt routine
--
-- Revision 1.4 2006/05/27 19:14:18 arniml
-- interrupt functionality added
--
-- Revision 1.3 2006/05/22 00:02:36 arniml
-- instructions ININ and INIL implemented
--
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem1_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem1_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instr_Mem1_exdes;
ARCHITECTURE xilinx OF Instr_Mem1_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instr_Mem1 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instr_Mem1
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem1_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem1_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instr_Mem1_exdes;
ARCHITECTURE xilinx OF Instr_Mem1_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instr_Mem1 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instr_Mem1
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Testbench: Testbench for arith_prefix_and.
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith.prefix_and
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity arith_prefix_and_tb is
end arith_prefix_and_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.simulation.ALL;
architecture tb of arith_prefix_and_tb is
-- component generics
constant N : positive := 8;
-- component ports
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic_vector(N-1 downto 0);
begin -- tb
-- component instantiation
DUT: entity PoC.arith_prefix_and
generic map (
N => N
)
port map (
x => x,
y => y
);
-- Stimuli
process
begin
-- Exhaustive Testing
for i in NATURAL range 0 to 2**N-1 loop
x <= std_logic_vector(to_unsigned(i, N));
wait for 10 ns;
for j in 0 to N-1 loop
tbAssert((y(j) = '1') = (x(j downto 0) = (j downto 0 => '1')),
"Wrong result for "&integer'image(i)&" / "&integer'image(j));
end loop;
end loop;
-- Report overall result
tbPrintResult;
wait; -- forever
end process;
end tb;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Testbench: Testbench for arith_prefix_and.
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith.prefix_and
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity arith_prefix_and_tb is
end arith_prefix_and_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.simulation.ALL;
architecture tb of arith_prefix_and_tb is
-- component generics
constant N : positive := 8;
-- component ports
signal x : std_logic_vector(N-1 downto 0);
signal y : std_logic_vector(N-1 downto 0);
begin -- tb
-- component instantiation
DUT: entity PoC.arith_prefix_and
generic map (
N => N
)
port map (
x => x,
y => y
);
-- Stimuli
process
begin
-- Exhaustive Testing
for i in NATURAL range 0 to 2**N-1 loop
x <= std_logic_vector(to_unsigned(i, N));
wait for 10 ns;
for j in 0 to N-1 loop
tbAssert((y(j) = '1') = (x(j downto 0) = (j downto 0 => '1')),
"Wrong result for "&integer'image(i)&" / "&integer'image(j));
end loop;
end loop;
-- Report overall result
tbPrintResult;
wait; -- forever
end process;
end tb;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Wed Dec 14 12:20:57 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.4 2005/12/14 12:38:03 wig Exp $
-- $Date: 2005/12/14 12:38:03 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.4 2005/12/14 12:38:03 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug_tb is
end bug_tb;
-------------------------------------------------------------------------------
architecture test of bug_tb is
type t_test_vec is array (10 downto -1) of std_logic;
signal test_vec : t_test_vec := (others => '0');
-- clock
signal Clk : std_logic := '1';
procedure pr_vec (
vec : in std_logic_vector) is
begin -- procedure pr_vec
for i in vec'range loop
report "bit: " & integer'image(i) & "=" & std_logic'image(vec(i)) severity note;
end loop; -- i
end procedure pr_vec;
begin -- test
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until rising_edge(Clk);
pr_vec(std_logic_vector(test_vec));
wait;
end process WaveGen_Proc;
end test;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug_tb is
end bug_tb;
-------------------------------------------------------------------------------
architecture test of bug_tb is
type t_test_vec is array (10 downto -1) of std_logic;
signal test_vec : t_test_vec := (others => '0');
-- clock
signal Clk : std_logic := '1';
procedure pr_vec (
vec : in std_logic_vector) is
begin -- procedure pr_vec
for i in vec'range loop
report "bit: " & integer'image(i) & "=" & std_logic'image(vec(i)) severity note;
end loop; -- i
end procedure pr_vec;
begin -- test
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until rising_edge(Clk);
pr_vec(std_logic_vector(test_vec));
wait;
end process WaveGen_Proc;
end test;
|
-------------------------------------------------------------------------------
-- Title : Writeback instruction's result
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Writeback.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-16
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Writes back a MIPS instruction result into the register file
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-16 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
-------------------------------------------------------------------------------
entity Writeback is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
NB_REGISTERS : positive := 34
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic; -- stall current instruction
kill_req : in std_logic; -- kill current instruction
i_reg1 : in register_port_type;
i_reg2 : in register_port_type;
i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_is_jump : in std_logic;
o_reg1 : out register_port_type;
o_reg2 : out register_port_type;
o_is_jump : out std_logic;
o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Carry-over signals
i_instr_tag : in instr_tag_t;
o_instr_tag : out instr_tag_t;
-- Debug signal
i_dbg_wb_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_wb_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0)
);
end entity Writeback;
-------------------------------------------------------------------------------
architecture rtl of Writeback is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal reg1 : register_port_type;
signal reg2 : register_port_type;
signal is_nop : boolean;
signal last_is_jump : std_logic;
signal last_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal last_instr_tag : instr_tag_t;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
is_nop <= true when i_reg1.we = '0' and i_reg2.we = '0' and
not i_instr_tag.is_branch and not i_instr_tag.is_ja and
not i_instr_tag.is_jr else false;
process(rst, clk, stall_req)
begin
if rst = '1' then
reg1.we <= '0';
reg2.we <= '0';
o_instr_tag <= INSTR_TAG_NONE;
last_instr_tag <= INSTR_TAG_NONE;
last_is_jump <= '0';
last_jump_target <= (others => 'X');
elsif rising_edge(clk) then
if kill_req = '1' then
reg1.we <= '0';
reg2.we <= '0';
o_is_jump <= '0';
o_jump_target <= (others => 'X');
o_instr_tag <= INSTR_TAG_NONE;
elsif stall_req = '0' then
if not is_nop then
last_instr_tag <=
get_instr_change_is_branch_taken(i_instr_tag, i_is_jump = '1');
last_is_jump <= i_is_jump;
last_jump_target <= i_jump_target;
end if;
-- Branch delay slot of 1 :
--- If branch or jump, delay setting o_is_jump and o_jump_target to
--- the next no-NOP instruction
--- If not, forward as is.
if (last_instr_tag.is_branch or last_instr_tag.is_ja
or last_instr_tag.is_jr) and not is_nop then
-- Falsify the outputs to fake the jump/branch happens on the next
-- after jump/branch instruction, ie. delay slot of 1.
-- Transfer the jump and the writeback instruction together
-- The o_instr_tag is changed from the instruction just after the
-- branch to the instruction branch, for branch prediction.
o_is_jump <= last_is_jump;
o_jump_target <= last_jump_target;
o_instr_tag <=
get_instr_change_is_branch_taken(
get_instr_change_is_branch(
get_instr_change_is_ja(
get_instr_change_is_jr(i_instr_tag, last_instr_tag.is_jr),
last_instr_tag.is_ja),
last_instr_tag.is_branch),
last_instr_tag.is_branch_taken);
elsif (i_instr_tag.is_branch or i_instr_tag.is_ja
or i_instr_tag.is_jr) then
-- As the jump information is kept in last_*, wipe out any
-- jump/branch sign from this instruction, as it will be reapplied on
-- the next one.
o_is_jump <= '0';
o_jump_target <= (others => 'X');
o_instr_tag <=
get_instr_change_is_branch_taken(
get_instr_change_is_branch(
get_instr_change_is_ja(
get_instr_change_is_jr(i_instr_tag, false),
false),
false),
false);
else
-- Here there wasn't a "jump/branch" kept nor on the input
-- instruction, so forward normally everything.
o_is_jump <= i_is_jump;
o_jump_target <= i_jump_target;
o_instr_tag <= i_instr_tag;
end if;
reg1 <= i_reg1;
reg2 <= i_reg2;
end if;
end if;
end process;
debug : process(rst, clk, stall_req, kill_req)
begin
if rst = '1' then
o_dbg_wb_pc <= (others => 'X');
elsif rising_edge(clk) and kill_req = '1' then
o_dbg_wb_pc <= (others => 'X');
elsif rising_edge(clk) and stall_req = '1' then
elsif rising_edge(clk) then
o_dbg_wb_pc <= i_dbg_wb_pc;
end if;
end process debug;
o_reg1 <= reg1;
o_reg2 <= reg2;
end architecture rtl;
-------------------------------------------------------------------------------
|
--Módulo para converter um dado para mostrar no display 7 segmentos da placa DE2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
|
--Módulo para converter um dado para mostrar no display 7 segmentos da placa DE2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seven_seg_decoder is
port(
data: in STD_LOGIC_VECTOR(3 downto 0);
segments: out STD_LOGIC_VECTOR(6 downto 0)
);
end;
architecture seven_seg_decoder_arch of seven_seg_decoder is
begin
process(data)
begin
case data is
when X"0" => segments <= not "0111111";
when X"1" => segments <= not "0000110";
when X"2" => segments <= not "1011011";
when X"3" => segments <= not "1001111";
when X"4" => segments <= not "1100110";
when X"5" => segments <= not "1101101";
when X"6" => segments <= not "1111101";
when X"7" => segments <= not "0000111";
when X"8" => segments <= not "1111111";
when X"9" => segments <= not "1101111";
when X"A" => segments <= not "1110111";
when X"B" => segments <= not "1111100";
when X"C" => segments <= not "0111001";
when X"D" => segments <= not "1011110";
when X"E" => segments <= not "1111001";
when X"F" => segments <= not "1110001";
when others => segments <= not "0000000";
end case;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
case A is
when '0' =>
case B is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
when '1' =>
case C is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
end case;
end process;
end behv;
|
-- 3-D Ram Inference Example (Single port)
-- Compile this file in VHDL2008 mode
-- File:rams_sp_3d.vhd
library ieee;
use ieee.std_logic_1164.all;
package mypack is
type myarray_t is array(integer range<>) of std_logic_vector;
type mem_t is array(integer range<>) of myarray_t;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypack.all;
entity rams_sp_3d is generic (
NUM_RAMS : integer := 2;
A_WID : integer := 10;
D_WID : integer := 32
);
port (
clk : in std_logic;
we : in std_logic_vector(NUM_RAMS-1 downto 0);
ena : in std_logic_vector(NUM_RAMS-1 downto 0);
addr : in myarray_t(NUM_RAMS-1 downto 0)(A_WID-1 downto 0);
din : in myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0);
dout : out myarray_t(NUM_RAMS-1 downto 0)(D_WID-1 downto 0)
);
end rams_sp_3d;
architecture arch of rams_sp_3d is
signal mem : mem_t(NUM_RAMS-1 downto 0)(2**A_WID-1 downto 0)(D_WID-1 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
for i in 0 to NUM_RAMS-1 loop
if(ena(i) = '1') then
if(we(i) = '1') then
mem(i)(to_integer(unsigned(addr(i)))) <= din(i);
end if;
dout(i) <= mem(i)(to_integer(unsigned(addr(i))));
end if;
end loop;
end if;
end process;
end arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_ibea_entity;
ARCHITECTURE hal_ibea_description OF hal_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "0000000000000000000000000000101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_ibea_description; |
--------------------------------------------------------------------------------
-- ion_shifter.vhdl -- combinational barrel shifter
--
--------------------------------------------------------------------------------
-- Copyright (C) 2011 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received A_I copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity ION_SHIFTER is
port(
-- data input
D_I : in std_logic_vector(31 downto 0);
-- shift amount
A_I : in std_logic_vector(4 downto 0);
-- shift function: {0=sll,1=sla(unused),2=srl,3=sra}
FN_I : in std_logic_vector(1 downto 0);
-- shift result
R_O : out std_logic_vector(31 downto 0)
);
end;
architecture small of ION_SHIFTER is
signal i_rev, o_rev : std_logic_vector(31 downto 0);
signal ext : std_logic_vector(31 downto 0);
type t_s is array(0 to 5) of std_logic_vector(31 downto 0);
signal s : t_s;
begin
-- The barrel shifter needs to shift left and right. This would usually
-- require two parallel barrel shifters (left and right) and an output mux
-- stage. Instead, we're gonna use A_I single left shifter, with two
-- conditional bit-reversal stages at input and output.
-- This will increase the LUT depth (and thus the delay) by 1 LUT row but
-- we'll cut the area by 4/11 more or less (depends on how many dedicated
-- muxes vs. LUTs the synth will use).
-- The barrel shifter can account for as much as 1/4 of the CPU area
-- (excluding mult/div unit) so it makes sense to be cheap here if what we
-- want is A_I small core.
-- NOTE: this logic may or may not be in the critical delay path of the
-- core, depending on the cache implementation. See your synthesis report.
-- Reverse input when shifting right
input_reversed:
for i in 0 to 31 generate
begin
i_rev(i) <= D_I(31-i);
end generate input_reversed;
s(5) <= i_rev when FN_I(1)='1' else D_I;
-- Sign extension / zero extension
ext <= (others => D_I(31)) when FN_I(0)='1' else (others => '0');
-- Build left barrel shifter in 5 binary stages as usual
shifter_stages:
for i in 0 to 4 generate
begin
with A_I(i) select s(i) <=
s(i+1)(31-2**i downto 0) & ext(2**i-1 downto 0) when '1',
s(i+1) when others;
end generate shifter_stages;
-- Reverse output when shifting right
output_reversal:
for i in 0 to 31 generate
begin
o_rev(i) <= s(0)(31-i);
end generate output_reversal;
R_O <= o_rev when FN_I(1)='1' else s(0);
end architecture small;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLROM_3_15.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_15
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLROM_3_15
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.OFDM_transmitter_pkg.ALL;
ENTITY TWDLROM_3_15 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_vld : OUT std_logic
);
END TWDLROM_3_15;
ARCHITECTURE rtl OF TWDLROM_3_15 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_15_re_tmp <= twdlIn_re;
twdl_3_15_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_15_re <= std_logic_vector(twdl_3_15_re_tmp);
twdl_3_15_im <= std_logic_vector(twdl_3_15_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_15_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_15_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
library verilog;
use verilog.vl_types.all;
entity Rounding is
port(
clk : in vl_logic;
res : in vl_logic;
shift : in vl_logic_vector(27 downto 0);
incre : in vl_logic_vector(8 downto 0);
exp_result : out vl_logic_vector(7 downto 0);
fra_result : out vl_logic_vector(27 downto 0);
result : out vl_logic_vector(31 downto 0);
overflow : out vl_logic
);
end Rounding;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity umul23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (45 downto 0)
);
end entity umul23;
architecture rtl of umul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (in_vec : in std_logic_vector);
end entity;
architecture rtl of test is
signal A : natural;
begin
gen2 : if in_vec'length <= 2 generate
A <= 2;
end generate;
gen3 : if in_vec'length > 2 generate
A <= 3;
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (in_vec : in std_logic_vector);
end entity;
architecture rtl of test is
signal A : natural;
begin
gen2 : if in_vec'length <= 2 generate
A <= 2;
end generate;
gen3 : if in_vec'length > 2 generate
A <= 3;
end generate;
end architecture;
|
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